1. Field of the Invention
This invention relates in general to magnetic storage systems, and more particularly to combined read and write VCO for data channels.
2. Description of Related Art
In computer systems, information is stored on magnetic storage systems such as hard drives. Data is stored in a series of spiral or concentric rings known as tracks. The data includes streams of magnetic polarity transitions on the disk surface. A number of schemes are used to detect these transitions and data.
One data detection method is a peak detection system. Peak detection ensures the accurate reading of the magnetic transitions that encode the bits on a disk. These magnetic transitions are given a 1 or 0 value. In reading two adjacent transitions, i.e. two adjacent 1s, the signals can interfere with each other and cancel each other out. To avoid this "inter-symbol" interference the data must be encoded which results in a coded data string that is about 50% longer than an uncoded string. This extended code takes up disk space and limits bit density.
PRML overcomes this by comparing a data string with all known possible data strings to determine its identity. A PRML channel can be used to achieve high data density in writing and reading digital data on magnetic recording disks. This technique takes inter-symbol interference into account rather than tying to eliminate it. The result is a far more efficient coding scheme that permits more bits to be encoded on a track.
The actual control mechanism for PRML is in the selection of the partial response targets or polynomials which are chosen. In a PRML channel, the incoming signal from the preamplifier is first equalized and then sampled according to the partial response regimen selected. These samples are then fed to the maximum likelihood sequence detection circuitry, commonly a Viterbi detector, which identifies a sequence of bits read from the drive that would be the most likely to cause this sampled pattern. Since detection is applied to a sequence of bits rather than a series of individual bits, the PRML detector does a much better job of resolving marginal bit transitions, and therefore tolerates a much higher bit density (hence lower SNR) without increasing bit error rates.
PRML channels require timebase generation during write operations and timebase capture during read operations. Previous channel designs used separate voltage controlled oscillators (VCOs) for read and write operations. The write VCO (timebase generator) runs the entire time the channel is enabled due to its slow response. The write VCO can not be stopped during a read because, after the read ends and the write VCO is restarted, the write VCO takes too long to reacquire an accurate timebase, thus forcing the DASD product to wait until the channel was ready before performing a write operation and having an adverse effect on performance.
The read VCO (timebase capture) also runs the entire time the channel is enabled due to the need for quick timing capture at the beginning of every read. When the channel is not reading, the read VCO is locked to the write VCO, so the read VCO is at the correct frequency when a read begins. This substantially improves the time required to capture the frequency and phase of the signal being read, since the frequencies should nearly match, even though spindle speed tolerance can induce a difference.
Thus, previous channels have all used separate read and write VCOs for performance reasons, but all suffer from the same problems. For example, excess power is used during read operations due to the write VCO. Also, providing two VCOs and associated circuitry increases the chip size. Further, increased clock noise coupling occurs during read operations due to the write VCO
It can be seen that there is a need for a combined read and write VCO for data channels.